1. Field of the Invention
This invention relates generally to the system architecture and method for a time recovery system. More particularly, this invention relates to a system architecture to achieve a fast time acquisition by utilizing independent dual-loop with frequency and phase locking operations capable of performing a continuous automatic frequency trimming.
2. Description of the Prior Art
As greater amounts of data and signals are now being transmitted among the networked systems, application of conventional time-acquisition techniques in such networked systems often becomes a bottleneck in the operation of high speed communication due to the elapsed-time required in performing the task of time-recovery. Another difficulty often encountered in such communication systems by the use of the conventional time-acquisition system is the frequency instability. When there is a frequency drift either for the transmitting or the receiving system, mismatches or errors in communication may occur. Such difficulties are becoming even more serious when the frequency, i.e., the data rate, is rapidly increasing as the modern communication and computer technology push the communication systems to achieve unprecedented high speed.
In order to perform the task of time acquisition, or sometimes referred to as `time synthesis`, the system clock of the receiving system must be synthesized with the incoming signals. The signal receiving system must be able to detect the frequency and the phase of the incoming signals and performs a frequency and phase synthesis in order to accurately capture the incoming signals. The task of `time synthesis` becomes quite complicated because there is a close interdependency between the detection and locking of the receiving system's frequency and phase to that of the incoming signals. When there is an error in detecting or locking to either the frequency or phase, a corresponding error is generated which could soon leads to signal divergence and frequency or phase instabilities which often hinder a receiving system from accurately capturing the incoming signals.
Several types of time recovery systems are commonly applied in the prior art to achieve this frequency and phase synthesis task. The first type is the inter-dependent continuous dual frequency locking loop (FLL) and phase locking loop (PLL) system. A basic architecture of an inter-dependent dual FLL/PLL system 10 is shown in FIG. 1. The incoming input signals 15 are received simultaneously by a phase detector 20 and a frequency detector 25. The detected signals are then processed by a PLL loop filter 30 and a FLL loop filter 35. The results generated from these filters are then processed by a summing operating means 40 to generate an inter-loop error signal for inputting to a voltage controlled oscillator 45 to generate an output signal 50.
AT&T's T7035 Clock Recovery Circuit represents such a system (Data Sheet, Microelectronics AT&T, July 1991). It operates over a frequency range of 51.5 to 235 MHz using a single plus or minus five volts supply. The overall circuit architecture includes a phase and frequency locked loop to extract the clock from the input data. The basic operation is managed by a low-gain PLL composed of a phase detector, a variable length current controlled oscillator (CCO), and a frequency divider circuit. Such a system has a difficulty caused by the dual loop interferences due to the inter-dependencies and coupling of loop operations. Because of the complicate inter-dependencies of loop parameters between these two loops, the inter-loop interferences often make the optimization of loop parameters difficult to achieve. Additionally, due to the inter-loop interferences, the time required for either of the loops to accurately lock on to the input signal is increased which causes the slowdown of the acquisition time.
A second type of time recovery system is a digital-frequency-trim with PLL system. FIG. 2 shows in block diagram a basic system architecture of this type of systems wherein a digital-frequency-trim with PLL system 60 has a phase detector 65 to receive the input signal 62. The detected signal is then processed by a loop filter 70 on the phase lock loop (PLL). The system 60 also includes a reference clock 75 which generates a reference clock signal to a frequency detector 80. The detected frequency is controlled by a digital control logic 85. The results generated by the digital control logic 85 and the PLL loop filter 70 are then processed by a summing operation means 90 to generate an error signal to adjust a voltage control oscillator (VCO) to generate an output signal 100.
Caldwell et al. disclose such a time acquisition system in U.S. Pat. No. 4,580,107, entitled `Phase Lock Acquisition System having FLL for Coarse Tuning and PLL for Fine Tuning` (issued on Apr. 1, 1986). Caldwell et al. applied a system architecture which is capable of acquiring phase lock from incoming signals which may have large frequency errors. A combination of analog and digital circuits are used wherein the phase locked loop is used as a tracking filter. The filter employs a wideband frequency discriminator and digital positioning circuit to acquire phase lock. A digital control is used in the FLL to tune the VCO within acquisition range of the wide-band frequency discriminator. The frequency is trimmed into the PLL capture range before the timing recovery system operates and the whole communication system using this time recovery system has to be on hold during this frequency trimming process.
This type of architecture requires a reference clock and the associated frequency trimming circuits. A crystal is usually used as a reference clock for trimming purposes and a digital to analog converter (DAC) is usually implemented in configuring the trimming circuit. It should be noted that the least significant bit for the DAC corresponding to the frequency resolution has to be at least smaller than the pull-in range of the system. This requirement increases the complexity of the DAC's design, especially when the DAC design is to be implemented by a very large scale integrated (VLSI) circuit for a high speed communication system.
Because of the above design considerations, this type of time recovery system requires not only an external clock to provide a reference clock signal, but the design and fabrication of such systems are more complex and generally would occupy larger volume. This type of system also has a disadvantage in that the tuning is limited by the discrete resolution of the frequency trimming circuits. Additionally, since the PLL and the frequency trimming loop are coupled, the loop parameters are highly inter-dependent due to the coupling of the summing operation means 90, and the difficulties of inter-loop interferences as encountered by the previous dual loop system also limit the speed and optimization of this type of time recovery system.
A third type of time acquisition system is similar to the digital trim PLL system described above except that instead of using a single VCO, this type of timing synthesis circuits uses two VCOs. Malaviya discloses in U.S. Pat. No. 4,131,861, entitled `Variable Frequency Oscillator System Including Two Matched Oscillators Controlled by a Phase Locked Loop`, (Issued on Dec. 26, 1978) a variable frequency oscillator for providing a frequency output which is near the output of a highly stable crystal oscillator. The output of the crystal oscillator and the output of one of the variable frequency oscillators are provided to a phase locked loop which in turn provides a correctional signal to both variable frequency oscillators. This causes the first VCO to lock in with the reference frequency so that its output frequency becomes identical with the reference frequency. This further causes the second VCO to have an output frequency that is highly stable about the center reference frequency of the crystal oscillator. The output of the second VCO can be used as the system clock for the local system. In addition to the same difficulties caused by the dual loop interferences and discrete tuning as mentioned above, this type of systems also requires an external reference clock.
This basic technique is used by Thompson and Lee as described in their paper entitled `A BiCOMS Receiver/Transmit PLL Pair for Serial Data Communication` (IEEE 1992, Custom Integrated Circuit Conference) the phase locked loops for frequency synthesis and clock recovery in serial data communication. A master-slave loop architecture is constructed which uses the frequency reference for the transmit loop to set the center frequency of the receive loop. The transmit frequency synthesis loop serves as the master loop which comprises a first VCO, a phase-frequency detector, pre-scaler, and loop filter to generate the transmit dock from an external reference clock. The receive loop is set up as the slave loop which comprises a second VCO, a phase detector, and a loop filter. The receive loop uses the transmit loop control voltage as a coarse adjustment to its input to the second VCO. This assures the central frequency of the receive loop is within the VCO mismatch of the input data rate.
Even though this technique generates a highly stable output frequency that is very close to the central frequency of the reference clock signal, this type of architecture suffers the disadvantage that it requires an external clock. The additional hardware requirements add more complexities to the IC design and fabrication. The total volume of the signal processing device is also increased due to additional hardware requirements. Furthermore, the same limitations on acquisition speed imposed by the inter-loop interferences cannot not be resolved by this type of time-recovery system.
Therefore, there is still a need in the art in the design and fabrication of time recovery systems to have a novel and improved system architecture and signal processing techniques that would resolve the difficulties and remove the limitations described above. Namely, this system must be able to reduce and minimize the inter-loop interferences to improve the acquisition while maintaining a simple system architecture without unduly imposing extra complexities on the system design and hardware requirements.